Defragmentation of Tasks in Many-Core Architecture

Photonic Many-Core Architecture Study

Several recent device technology developments have been fundamentally changing the microprocessor architecture design space. These developments include photonic interconnects, feature size reduction, 3D fabrication, and aggressive energy management. These technologies create a large parameter space of possible future architectures. The focus of this talk and research effort is to demonstrate a ...

Microgrid - The microthreaded many-core architecture

Traditional processors use the von Neumann execution model, some other processors in the past have used the dataflow execution model. A combination of von Neuman model and dataflow model is also tried in the past and the resultant model is referred as hybrid dataflow execution model. We describe a hybrid dataflow model known as the microthreading. It provides constructs for creation, synchroniz...

Many-core architecture for programmable hardware accelerator

Power-Aware Core Management Scheme for Heterogeneous Many-Core Architecture

OF THE THESIS Power-Aware Core Management Scheme for Heterogeneous Many-Core Architecture By Myoung-Seo Kim Master of Science in Computer Engineering University of California, Irvine, 2015 Professor Jean-Luc Gaudiot, Chair The main challenge in designing the future heterogeneous many-core architecture on the same chip is to provide a solution that has low power consumption, in addition to trade...

Efficient Execution of Dependent Tasks on Many-Core Processors

The increasing performance requirements of safety-critical real-time embedded systems made traditional single-core architectures obsolete. Moving to more complex many-core systems requires new techniques and tools for the certification of the embedded software. Timing and functional behaviours are subject to specific requirements of certification guidelines such as D-178B/C for avionics and ISO...